Fundamental Layout and Routing-Driven Noise Suppression & QCD Optimization
The Mechanics of “Fundamental Layout and Routing-Driven Noise Suppression“
FAQ
What exactly is “Layout and Routing-Driven Noise Suppression”?
It is a methodology that enhances EMC immunity at its core. Instead of relying on add-on components, we identify the specific „pathological areas“ vulnerable to noise and eliminate the root cause through strategic layout and routing modifications.
Is this applicable to any type of product or industry?
Yes, in principle, it is applicable to almost any design regardless of the industry, as our approach is based on fundamental physics. However, please note that in circuits with severe physical constraints, the scope of improvement may be limited. We do not guarantee the same level of results for every project.
We already identify causes and apply countermeasures daily. What makes your approach different?
The difference lies in our „analytical perspective“ and the „systematic process“ we use to reach a resolution—both of which operate on a fundamentally different level. Please refer to the following five key points.
Standard Approach:
Noise entry/exit points (Connectors and external interfaces).
External control terminals of each device (Reset, Interrupt, Enable/Disable pins, etc.).
Our Approach:
Structural vulnerabilities of the entire PCB (Note: We do not focus on noise entry/exit points at all.)
Standard Approach:
Because the input stage is the direct trigger that causes malfunctions.
Because applying countermeasures at the input terminals is considered the „standard“ of EMC design.
Our Approach:
Because those „structural vulnerabilities“ are the true root cause that weakens noise immunity across both EMI and EMS.
Standard Approach:
Adding off-the-shelf suppression components or modifying circuit constants.
Our Approach:
Eliminating the „structural vulnerabilities“ themselves.
“Now, imagine a situation where you have achieved some improvement through cumulative efforts, yet you still haven’t secured a stable pass—for example, an ESD test at 8kV where the product precariously fluctuates between passing and failing, leaving your compliance completely unstable.”
Standard Approach:
Adding even more suppression components and repeatedly attempting to “reinforce” the board by brute force.
Our Approach:
Serenely identifying other latent “structural vulnerabilities” and systematically applying the same radical countermeasures to achieve effortless, horizontal elimination.
Standard Approach:
Even after adding two or three more components, you likely won’t see any significant breakthrough in effectiveness.
Our Approach:
By optimizing the fundamental layout paths, your overall EMC Robustness will scale exponentially. Each layered countermeasure triggers a powerful positive synergy, causing your product’s immunity to skyrocket far beyond simple addition.
Negative Synergy
In simple circuits with ten or fewer components, the causal relationships between noise sources are clear, making identification straightforward.
However, as board complexity increases, multiple noise sources begin to interfere with one another, causing them to lose their independence. This is what we call „Negative Synergy.“ In this state—where the specific point you are addressing is constantly impacted by noise from other sources—individual component-based fixes become futile.
You likely follow the fundamental principles of circuit design and apply precise suppression to the most dominant noise source. Yet, you will find that the results are barely noticeable.
The reason is simple: the more noise sources there are, the more the „Negative Synergy“ (the negative force) overwhelms your „corrective action“ (the positive force). The improvement is essentially overwritten, making it impossible to perceive any reduction.
The measure you took is, without a doubt, the „Right Solution.“ However, because the effect remains „invisible“ under the weight of other noise, you simply cannot experience the breakthrough you deserve.
„If there were a measurement tool capable of completely isolating interferences and extracting the precise effect of the countermeasure you just applied, you would instantly see that your logic was correct. You could then horizontally deploy that solution and reach a final resolution. Unfortunately, no such instrument exists.“
As a result, your entire logic for EMC suppression collapses. You lose sight of your strategic direction and find yourself trapped within a ‚debugging labyrinth‘ with no clear way out.
„The more logical and disciplined an engineer you are, the deeper you will sink into this ‚EMC quagmire‘ where fundamental principles seem to fail—and the harder it becomes to find an exit on your own.“
Seal All Leaks Simultaneously!
The key to successful EMC suppression is removing negative factors all at once.
The Leaky Bucket Metaphor: Imagine a water bucket plagued with multiple distinct holes on its surface. No matter how much volume or power you continuously pour into the system from the top, the structure inherently fails to hold fluid because it continues to bleed energy from the bottom.
The Trap of Partial Fixes: If there are three separate leaks—A, B, and C—plugging only one single leak (A) will technically reduce the localized outward flow at that specific coordinate. However, as long as paths B and C remain wide open, the core systemic problem persists, and the bucket completely fails to fulfill its ultimate functional purpose.
Achieving Peak Performance: To restore the bucket’s “Maximum Performance” (zero leaks and perfect containment), you must ruthlessly identify, isolate, and seal all critical leakage points simultaneously. In the realm of EMC, treating only half of the non-compliant loops means your entire product remains dead on arrival at the compliance line.
Positive Synergy
„Linear“ Improvement Targeting Isolated Causes:
Countermeasures for isolated and simple noise sources are typically handled by adding components like EMI filters. In these cases, the effectiveness strictly follows the datasheet specifications?such as frequency response curves or „XX dB attenuation at XX Amps.“ This is merely a „Linear“ improvement, where the result is directly proportional to the component’s rated performance.
Explosive „Non-linear“ Results Beyond Prediction:
However, when you eliminate the root causes of Negative Synergy, the outcome far exceeds the „Linear“ predictions described above. It triggers an „Explosive Non-linear Effect“ where the entire board’s immunity is fundamentally transformed.
A Physical Inevitability Beyond Components:
Why is it explosive? Because the Negative Synergy was already causing non-linear degradation. Removing that negative force naturally unlocks a massive, non-linear surge in performance.
As a seasoned engineer, you likely see the conclusion: this methodology delivers a level of effectiveness that individual noise suppression components simply cannot achieve.
Complexity Breeds Excellence: The Spice Analogy
Positive countermeasures don’t just add up; they create a „Positive Synergy.“
The Spice Metaphor: Think of premium spices A, B, and C in a masterfully crafted curry. While each distinct spice adds its own unique aroma and localized flavor profile, combining all three elements simultaneously creates a rich, complex, and deeply layered “Umami” that is fundamentally impossible to achieve by simply adding or measuring their individual effects.
The Law of Signal Integrity: This is exactly how optimized return paths operate on a high-speed PCB. A single re-routed trace yields limited results, but the harmonious layering of interconnected reference planes multiplies your suppression power—unlocking a massive electromagnetic harmony that add-on filters can never replicate.
Real-World Modeling: Quantifying Negative and Positive Synergy
To capture the true operational reality of these physical dynamics, let us apply the concepts of negative synergy (The Bucket Metaphor) and positive synergy (The Curry Metaphor) directly to a real-world engineering crisis—a product currently failing its compliance tests inside an EMC laboratory.
Imagine you are currently conducting an ESD (Electrostatic Discharge) test, and the product falls short of the mandatory 8 kV compliance limit. However, suppose it has already been determined that there are exactly three critical coordinates on your PCB—Points A, B, and C—where our unique engineering model, Our Containing Methodology (Fundamental Layout and Routing-Driven Noise Suppression), can be deployed to systematically eliminate these structural vulnerabilities.
Assume each distinct countermeasure contributes 1,000 V of immunity on its own. Would the total system improvement be a simple arithmetic sum of 3,000 V?
The answer is an absolute no.
Because these root-cause architectural optimizations trigger a powerful “Positive Synergy,” the cumulative electromagnetic containment inherently defies simple addition. In actual practice, combining layers A + B might yield 5,000 V, while the harmonious execution of A + B + C causes the entire system’s immunity to skyrocket to a massive 10,000 V.
Breaking the Impasse: The Devastating Defeat and Radical Turnaround
When textbook methods fail and every conventional noise filter yields zero results, a hardware engineer faces total isolation.
Below is the unvarnished personal engineering journal of the exact day I hit a brick wall at 0.5 kV—and how abandoning standard industry assumptions unlocked a 15 kV breakthrough.
If your team is currently trapped in the dark against an invisible enemy, this story is dedicated to you.
The Reality of the Professional Environment
Back then, I worked for a high-end contract design firm where we handled the entire process from schematics to mass production in rapid 2-3 month cycles. We weren’t a small shop.
Our R&D division had eight groups, each with 5-6 hardware and software engineers.
Our PCB layout and mechanical departments were separate elite units. With over 80 developers and 50 licenses of Zuken CR-5000—Japan’s absolute premier enterprise CAD system for high-reliability tier-1 hardware engineering—we were a mid-to-large operation handling mission-critical projects for automotive, medical, telecommunications, and government sectors.
The Brutal Design Reviews (DR)
Operating as a matrix organization, every failure and piece of know-how was shared across teams.
Our quality checklists were massive.
The Design Reviews after schematics and layout were brutal. A single session with all department leaders lasted at least five hours—and no design ever passed on the first attempt.
All „standard“ EMC measures were, of course, already implemented to the highest degree from day one.
The Elite Layout Team
The PCB layout team consisted of pure professionals. They were so experienced that they could interpret EMC requirements directly from the schematics and implement optimal routing without needing a single instruction.
Target Product Profile
The Target Product: Professional Image Recorder
| PCB | 8-layer (FR-4), postcard-sized. |
| CPU | 32-bit ARM Core. |
| Memory | Flash ROM, DDR2, External SD Card. |
| Main Processor | FPGA (Xilinx Spartan-3) |
| Interfaces | Ethernet, USB, HDMI, UART. |
| Power | Dual system (AC adapter / Li-ion battery). |
| Display | ~5-inch TFT LCD. |
| Controls | Membrane switches connected via FPC. |
— The Moment of Truth: The First Test —
The Setup: Preliminary Bare-Board Testing
The enclosure wasn’t ready yet, but we conducted preliminary tests on the bare board to gauge our standing.
The LCD and membrane switches were hung loosely. Power was supplied via an AC adapter.
Initial Results: A Total Disaster
ESD (Contact Discharge): We started at the absolute minimum setting of 500V. One zap, and the system reset instantly. 100% reproducibility.
Radiated Emission: We were failing by +5 dB to +8 dB over the limit. It wasn’t just a specific frequency spike; the entire spectrum was a mess of protruding peaks across the whole band.
It wasn’t a matter of „fine-tuning“ anymore. We were facing a complete engineering roadblock.
The Reality: This is No Longer an Engineering Problem
The requirement was 8kV Air Discharge.
In the final product, the board would be encased, theoretically avoiding direct contact. However, the internal LCD frame would undoubtedly crackle with continuous parasitic discharge, just as we always feared.
Even if we could dodge the air discharge, the exposed metal frames of the external connectors meant there was no escaping the Contact Discharge.
And here we were, failing at a mere 500V.
This wasn’t a level where you could just „fix it“ by swapping a few EMI filters or capacitors.
The EMI (Radiated Emission) was equally a nightmare. Since the enclosure was plastic, the shielding effect was zero. I decided to put the emission problem aside for a moment—I had to face the monster in front of me first.
The Internal Conflict
- We followed every EMC best practice. Why is this happening?
- What was the point of those grueling 5-hour Design Reviews with the ‘Gods of Engineering’ (my seniors) and their confident mandates?
- Realistically, what else is left to do? Where is the space to add even one more component?
- Shielding a plastic case with conductive gaskets for a Class 2 device? That is complete nonsense—it would skyrocket the BOM cost and instantly ruin the project’s commercial viability.
- I had a gut feeling: Even if I added 1,000 more noise suppression parts blindly, the immunity wouldn’t budge. I had to change the fundamental approach.
The Futile „Best Practice“ Patchwork
I tried the textbook moves anyway. I changed component values without real conviction. I stacked varistors on top of capacitors (the „piggyback“ method) on signal lines.
The result? Zero effect.
The board mocked me with another instant reset at 500V.
Stepping Back to Think
I asked myself: “What is different about this board compared to the ones that passed before?”
- The components were incredibly dense. The surface layers were so packed you could barely squeeze in a single trace.
- This was our first 8-layer design.
- It was a Class 2 device—no chassis ground to dump the energy into.
Then, the fundamental question:
„Where does the static charge actually go from the point of injection, and exactly how does it trigger a system reset?“
The Breakthrough: The Architectural Turning Point
I shifted my perspective. I decided—with all due respect to the „Gods“ of the Design Review—to test a theory of my own. I implemented a modification at just one single location based on my new hypothesis.
The result?
The immunity jumped from 500V to 4kV instantly!
It worked. It was real.
I applied the same logic to every other vulnerable point I could identify.
The outcome was beyond compliance: it passed 15kV Air Discharge with ease.
I wanted to push it even further to find the true limit, but I stopped there—I didn’t want to risk destroying the only evaluation board we had.
The Side Effect: EMI Success
Out of curiosity, I ran the Radiated Emission test again in this state.
Average noise levels had dropped by 10 dB. Even at the worst peak (QP value), we had a -5 dB margin against the limit.
“Wait, why did this happen?” A -5 dB worst-case margin on a bare board was an incredible achievement.
Stripping Away the „Insurance“
As a final test, I began removing all those „standard“ EMC components I had desperately added earlier.
The 15 kV EMC Robustness remained rock solid. Just as I suspected, those cumulative components weren’t doing a single thing.
„This method is far more effective than fighting noise with components.“
Next, I tested EFT/B (Electrical Fast Transient/Burst). Before applying our methodology, the baseline board had failed at a mere 500 V in a bizarre way—only on the negative side of the normal mode. Now, with our architectural modifications in place, it cleared 2,000 V without a single flinch.
That “Certain Proof of Effect” I uncovered that day—by testing my own physical theory at a single coordinate point—became the definitive origin of the “Fundamental Layout and Routing-Driven Noise Suppression” services I provide to the global market today.
Strategic Margin Adjustment: „De-tuning“
The „Massive EMC Compliance Margin“ created through Our Methodology is a „Critical asset“—not only for ensuring product reliability but also for enabling further optimization.
However, attempting to implement every suggested countermeasure in the mass-production board may require a „Complete overhaul of the layout“, risking significant delays in the development schedule.
This is where „Strategic Margin Adjustment“ (De-tuning) becomes essential. By strategically „Trimming the excess margin“, we find the „Optimal balance between compliance and man-hours“ required for design modifications.
Design Revision Dynamics: Full Suppression vs. Strategic De-tuning
As shown in the diagram above, there is a clear „Trade-off“ between achieving a ‚massive design margin‘ and ‚minimizing „Development lead time“.‘
We visualize this correlation „To help you identify“ the „Optimal landing point“—balancing technical robustness with your specific business requirements and project schedules.
BEYOND COMPLIANCE: The Ultimate Value of EMC Optimization
Achieving Massive Robustness
The EMC consulting provided by this firm completely redefines the boundaries of traditional „add-on component troubleshooting.“
Substantive QCD Optimization
QUALITY: Robust Design Immune to Manufacturing Variances
Many engineering teams have endured the grueling nightmare of unstable prototypes fluctuating between passing and failing under identical test conditions. Relying heavily on discrete suppression components like ferrite cores only provides a superficial, highly limited attenuation effect. This methodology implicitly harbors a critical, permanent risk of dipping back below the compliance threshold due to subtle component tolerances or slight environmental fluctuations.
Our methodology intercepts and controls the physical noise generation mechanism at its very root. By addressing the root-cause on the layout plane, we guarantee „Massive Robustness“ from the early design stages? establishing an architecture that remains completely impervious to external environmental variations.
Consequently, this creates a robust design possessing exceptionally high tolerance against „manufacturing variances“ across long-term mass production lifecycles.
Enhancing design quality at its core is the only legitimate pathway to elevate the baseline reliability of the entire end product.
COST: Aggressive BOM Cost Reduction through Strategic De-tuning
The exact, triumphant moment your product achieves EMC compliance is not a signal to pack up—it is the ultimate window of opportunity for profit optimization.
Now that the dominant noise sources have been structurally eliminated via root-cause layout modifications, the localized suppression previously performed by defensive insurance components implemented in the initial default design becomes entirely redundant in almost all cases.
Identifying these „just-in-case“ components and contractually validating them as „excessive“ based on rigorous electromagnetic physics to leave them unpopulated—this is high-value engineering that permanently maximizes your product’s gross margin.
We deeply understand the immense organizational pressure to immediately proceed to the next product development stage. However, the unique opportunity to safely test these cost-saving measures exists only now—while the active chamber and measurement environment are directly in front of us.
Refusing to get swept away by the team’s temporary sense of relief that „passing equals the end,“ we proactively propose a rigorous, post-compliance „De-tuning assessment“ to verify which redundant components can be safely deleted to maximize mass production profits.
DELIVERY: Shrunk Lead Times via Balanced Margin Engineering
To fiercely protect your development timeline, we entirely reject reckless, academic „perfectionism“ that demands maximizing design margins at all costs.
True agility lies in striking the optimal engineering equilibrium: securing adequate EMC parameters through targeted margin adjustment while accelerating the official product release.
We pinpoint and propose that exact, high-efficiency landing zone, ensuring your product hits the global market on schedule.
CONCLUSION: Standing Beside the Hardware Warrior
We refuses to operate as a mere temporary „troubleshooter.“
Our ultimate mission is to safeguard your product’s quality (Q), optimize its manufacturing cost (C), secure your development timeline (D), and seamlessly bridge your prototype to the mass production phase. I dedicate my absolute professional expertise to driving this comprehensive excellence.
Why can I propose such deeply intrusive and radical design modifications?
Because I am a fellow hardware engineer who has lived in the exact same trenches.
The Critical Challenge of Defect Rectification:
Unlike software development, where a bug can be instantly recompiled or patched via tools, hardware offers no such comfort. In the hardware domain, rectifying a single defect demands spinning a new PCB spin, procurement of physical components, and assembly—a high-stakes process where a first-time pass is the unyielding, absolute requirement.
The Ultimate Obstacle in Defect Localization:
While a software defect can be clearly visualized through debuggers, a hardware defect remains inherently invisible during high-stakes EMC testing. Under active EMS (Electromagnetic Susceptibility) conditions, you cannot simply hook up probes or measurement instruments to analyze the issue without altering the very fields you are testing. Therefore, direct measurement is impossible; your only recourse is to comprehend the behavior of the entire system, deduce the structural vulnerabilities through pure electromagnetic intuition, and relentlessly resolve the failure through strategic trial and error.
The moment a prototype fails EMC compliance, your entire corporate world and professional network shift overnight.
Suddenly, you are cast into total isolation. Why? Because the harsh reality of hardware engineering dictating that outside of you—the primary architect—the boundary of liability is distinct, and nobody else knows how to alter the physics of your board. Will your peers from that beautifully integrated matrix organization step in to save you?
The answer is a cold, definitive “No.”
A world-class mechanical design expert cannot rewrite your digital schematics or execute micro-level electrical hardware modifications inside an EMC chamber; they are fundamentally powerless to intervene in a purely electronic failure mode.
What about the corporate illusion of „solving challenges through organizational synergy“? Will your fellow hardware team members rally beside you?
In my extensive tenure on the front lines, the statistical reality is near 100% non-cooperation. Perhaps this represents the uniquely suffocating „Kuuki“ (the unwritten social atmosphere) of the corporate environment in Japan where I was raised, and perhaps teams in countries with different cultures are inherently more collaborative. Yet, whether it is an unspoken consensus in Tokyo or a cold detachment in Munich, the result remains the same.
They might casually drift by your bench. They might offer a hollow nod of sympathy. But beneath the façade, the unspoken consensus is unyielding: “This is your failure, not mine.” In the gritty reality of corporate engineering, sticking one’s neck out for someone else’s structural crisis only risks dragging oneself into the line of fire. Consequently, they maintain a calculated distance.
Meanwhile, management—completely detached from the first principles of physics—can only repeat their desperate, empty mandates: „Accelerate the timeline“ or „Find an alternative workaround.“
When a high-stakes project faces a catastrophic crisis, human nature reveals itself to be profoundly cold and transactional.
Perhaps the most freezing realization is the silence from the rest of the organization. Even as the critical mass production deadline aggressively narrows, your stakeholders stop hounding you for daily updates. This isn’t out of kindness; it is because the seasoned operators know that no one else can resolve this deadlock. This silent withdrawal is the ultimate, cold-blooded reality of engineering. You are entirely on your own. You have only your own hands, your own intellect, and the unyielding laws of physics to engineer your way out of the dark.
You are forced to launch your designs into the dark, fighting an invisible enemy—relying solely on system behavior and raw electromagnetic intuition to deduce the root cause.
It is like tracking a “Predator” in the pitch black, under a level of psychological pressure that software engineers will never truly comprehend.
When a prototype fails EMC, the mental toll is crushing. You can go home, sleep, and wake up the next morning, but the reality never changes on its own: the noise spectrum remains unpassed.
In that moment of total isolation, you cannot simply turn your back and walk away. I deeply understand that for hardware engineers, there is no place to hide.
In Japan, we have an ancient proverbial idiom used to describe the absolute humiliation of fleeing from a losing battle or collapsing under overwhelming fear: 「尻尾を巻いて逃げる」 (Shippo-wo-maite-nigeru).
This deep cultural metaphor perfectly mirrors the classic Western martial expression used in high-stakes operational crises: to “cravenly desert under fire” or to “abandon the field” in the face of overwhelming pressure.
However, no matter how desperately you wish to 「尻尾を巻いて逃げる」, the cold, unyielding laws of physics governing your PCB will never allow you to escape; that relentless noise spectrum will follow you all the way into mass production.
I understand your deep design anxiety, and I respect your engineer’s pride.
I am not here to merely „force a pass“ through your final compliance line using superficial tricks. I am here to stand beside you at the test bench, decode the invisible physics of your board, and collaboratively engineer the ultimate, high-yield solution that empowers your global business.
Let us conquer the compliance line together.
EMC試験合格への抜本的対策と、得られた大幅なマージンをあえてデチューン（マイナス調整）することが最適解
抜本的対策の定義と概念
抜本的対策とは、何ですか？
ノイズ対策部品に頼るのではなく、ノイズに弱い病巣部を特定し、レイアウト変更によってそれを排除することで、EMC耐性を本質的に向上させる手法です
どのような案件にも適用可能ですか？
物理現象に基づいたアプローチであるため、概ね可能です。ただし、制約が多い回路は改善幅が小さくなることが多いため、全ての案件において同等の結果を保証するものではない点はご留意ください。
原因を特定して対策をすることは、普段からやっていますが、何が違うのですか？
問題に対する着眼点及び、対策のプロセスが異なります。以下参照下さい。
一般的な対策
ノイズの出入り口
各デバイスの外部制御端子（リセット，割り込み，enable/disable端子など）
弊所の対策
基板全体の弱い部分（※ノイズの出入り口には全く着目していません）
一般的な対策
誤動作を引き起こすキッカケとなるのが入力部だから。
そこに対して対策を行うことが基本であるから。
弊所の対策
その「弱い部分」がEMI，EMS問わずノイズ耐性を弱くしているから。
一般的な対策
市販のノイズ対策部品を実装する，回路定数を変える。
弊所の対策
その「弱い部分」を取り除く。
ここで、そこそこのマージンが得られたけど、まだ合格規格値に届かないとします
一般的な対策
追加で部品を付けて補強する。
弊所の対策
他に弱い部分がないか探して同様の対策をする。
一般的な対策
おそらく対策部品を2つ、3つ付けたところで効果は変わらないでしょう。
弊所の対策
「弱い部分」という原因を取り除くので、それに比例して効果は現れます。
効果の度合いは基板毎に異なりますが、やればやるほど確実に耐性はアップします
大幅なマージンを獲得したEMC対策の実績例
弊所がこれまでに手掛けた対策の一例を紹介します。
静電気試験（ESD）
対策前：0.5kV で誤動作
対策後：15kV クリア（要求規格：8kV）
放射妨害電界強度試験（RE:Radiated Emission）
対策前：合格ラインに対しQP値で-2〜3dB の限界値（不合格リスクが非常に高い）
対策後：-10〜15dB の十分なマージンを確保
■当時勤めていた会社
設計，製造を専門で請負う会社に在籍していました。設計，評価から製造までのプロセスを2,3ヶ月周期でこなすといった業務でした。
会社の規模は、開発部門が８グループあり、各々のグループにはハードとソフトのメンバーがそれぞれ５，６人で構成されていました。
パターン設計と機構設計部門は独立して1部門づつ、各々６人程度。開発人員全体としては管理部門も入れると80人規模。CADは回路設計が図研のCR5000のSDで、パターン設計がCR5000のBD，PWSでフローティングライセンスは50個程運用していたため、中規模以上の設計会社だと思います。
クライアントの業種は自動車，FA，医療，通信，警備，官公庁と様々でした。
■デザインレビュー（DR）の精度
この複数の業界に接することができるメリットを活かし、不具合やノウハウは常に開発クループを横断し横串で情報共有されていました。マトリックス組織の理想の形でした。
その分、情報共有事項はどんどん増え、設計品質を担保するチェック項目は尋常ではないボリュームでした。
回路設計後とパターン設計後にはDRがあり、全部門のリーダーからチェックされる非常に厳しいものでした。回路DRは初回最低5時間はかかっており、まず初回で終わることはありませんでした。
当然の如く基本的なEMC対策は施されてます。
■パターン設計
配置配線、レイアウトのみを専門で行っているプロ集団でした。EMC対策に関して特別な指示をしなくとも回路図から勝手に読み取って反映してくれるレベルです。
■当時、設計していた製品の紹介
製品カテゴリー：業務用の画像録画再生装置
| 基板構成 | 8層基板（FR-4）でハガキ大のサイズ1枚 |
| CPU | ARMコア 32bit |
| メモリ | Flash，DDR，外部SDカード |
| 他の主なプロセッサ | FPGA（Xilinx Spartan-3） |
| I/F | 有線LAN，USB，HDMI，UART |
| 電源 | ACアダプタによるDC給電とリチウムイオン電池駆動の２系統 |
| 表示部 | 5インチ程のTFT液晶パネル |
| 操作部 | ５，６個のメンブレンシートスイッチをフレキシブル基板で接続 |
～いざEMC試験に望む～
■初回試験
まだ筐体（エンクロージャー）が出来上がっておらず最終形態での試験はできないが、当たりをつける目的で裸基板のまま静電気試験と放射妨害電界強度の試験を行った。
筐体ケースが無い状態で液晶とメンブレンスイッチは宙ぶらりんで適当に配置。電源はACアダプタによる給電で行った。
■初回のEMC耐性
静電気試験は基板に直接（接触放電）で行った。手始めに設定下限の500Vで印加したら一発でリセットがかかり不合格。再現率100％。
放射妨害電界強度試験は基準値より+5dB～+8dBほどオーバで不合格。どこの帯域が弱いとかウンヌンのレベルではない。帯域全体を通してスペクトルが突出しまくりで総じて不合格。
■…話にならん
ESDは気中8kVを要求されている。
製品最終形は、筐体ケースで基板は覆われ外部に露出されないため静電気は飛ばずに済む（接触放電は回避でき、逃げることができる）が、まちがいなく液晶のフレーム部でいつもどおりパリパリと音を立てて放電するだろう。
その気中放電は回避できても、外部コネクタの外枠金属は露出しているので接触放電からは逃げられない。
たった500Vで落ちている。これはノイズ対策部品でどうのこうの耐性を上げる話しではない。
EMIも頭が痛いが、樹脂筐体なのでシールド効果はゼロ。つまり「筐体によるシールド効果は皆無と思って良い」。ここは一旦、放射妨害は忘れよう。
■ここで感じたこと
- 『そこそこのEMC対策をしているのに、なぜだ。。。』
- 『DRの
神々ども（…いや、諸先輩方）の自信満々のオラオラ指示（…いや、アドバイス）は一体なんだったのか？』 - 『現実的に、これ以上どんなEMC対策をどこにするのだ？思いつかないし、追加部品を乗せるスペースもほとんどない』
- 『そもそも、何が悪いのかがわからない』
- 『EMIは筐体側でガスケット？筐体シールド？…-10dB程度確保するためにどんだけ分厚いガスケットを入れるのだ…考えたくない、どんどん製品コストが上がり目も当てられない。そもそも筐体アースがないClass2、その方向性はナンセンス、何か進んでいる方向を間違えている』
- 『仮にノイズ対策部品を闇雲に1000個付けたとしても、きっと耐性は上がらない予感がする。アプローチの方法を変えなければ…』
■やっつけで、お約束の一般的な追加対策
一応定石どおりやってみた。ノイズ対策部品の根拠のない定数変更。信号ラインのコンデンサにバリスタをおんぶ（親亀子亀）実装 。しかし、全く効果なし。
嘲笑うかのように500Vリセット。
■落ち着いて考えてみた
いつもの（合格してきた）他の基板との差は何だ？
- 今回は実装部品が密集しすぎている。表層（部品面,ハンダ面にほとんどパターンが引けないレベル）
- 8層基板は初めて
- AC100V金属筐体系のアース付き製品ではなくClass2［電撃に対する保護の話です］
- そもそも、静電気は印加した場所から「どこに回って、どうやって悪さをして、リセットを引き起こすのか？」
■【重要】転機
視点を変え、DRの神々（…諸先輩方）には申し訳ないが、独自の観点・理論で1箇所だけ試しで対策をしてみた。
なんと、静電気試験の耐性が一気に4kVまで上がった。
明らかに効果があったので、他に考えられる箇所全てに対策をしたら、結果、規格値合格どころか気中放電で+15kVまで合格した。
もっと印加電圧を上げて実力を見てみたかったが、限界試験をする状況ではないし、むやみに評価基板を壊したくないのでここでストップ。
■同時にEMIも…
この状態で試しに放射妨害の測定をしてみたところ、平均して-10dBは下がっている。最悪のQP値でも規格値から-5dBは確保できている。「なんだ？この差は？」ワースト-5dBは、なかなか良い出来である。
■一般的な対策を削除
試しに、先程やっつけで行ったEMC対策を取り外していった。もちろん大幅な15kVマージンは残ったままであった。案の定、効いていない
『この方法、ノイズ対策部品でEMC耐性を上げるより、遥かに効果が高い』
続けて、社内でプレ試験可能なEFT/B。初回は500Vで落ち、しかもノーマルモードのマイナス側のみ落ちるという不可解が現象であったが、全く問題なく2000Vクリアーした。
あの時、独自の観点・理論で1箇所だけ試しで対策して得た「確かな効果」
それが現在、弊所が提供している「抜本的対策の原点」となっています
以上
マージン調整（デチューン）
抜本的対策によって創出された「大幅なマージン」は、製品の信頼性を担保する極めて重要な資産です。
しかし、対策案のすべてを量産基板に反映しようとすれば、基板レイアウト（パターン設計）の大幅な見直しを要し、開発スケジュールを圧迫するリスクを孕んでいます。
そこで重要となるのが、得られたマージンを戦略的に削り、設変工数とのバランスを図るマージン調整(デチューン)という考え方です。
イメージ図
上図のように、「大幅なマージン」と「開発期間の短縮」はトレードオフの関係にあります。
弊所はこの相関関係を可視化し、貴社の状況に合わせた「最適な着地点」を見極めます。
まとめ：EMC最適解がもたらす価値
圧倒的な安定度
弊所が提供するEMCコンサルティングは、従来の「対症療法」とは一線を画します
EMC試験において、合格と不合格を繰り返す不安定な状況に苦慮された経験はないでしょうか。フェライトコア等の対策部品に頼る手法は、その減衰効果が限定的であり、わずかな個体差や環境変化で合格ラインを下回るリスクが常に内在しています。
弊所は、ノイズの発生機序そのものを物理的に制御するアプローチをとります。それにより、環境変化に左右されない「圧倒的な安定度」を設計段階から担保します。
本質的なQCD向上
Quality : ロバスト設計：バラツキに強い設計（Robust Design）
弊所が提唱する「抜本的対策」は、ノイズの源流に直接介入します。
これにより、個々の部品が持つ定数誤差や温度特性による影響を最小限に抑え込み、部品の個体差によってノイズ耐性が不安定になるフェーズを脱却します。
結果として、量産期間が長期に及ぶ中で発生する「製造バラツキ」に対しても、極めて高い耐性を持つ設計（ロバスト設計）が確保されます。
設計品質の根本的な向上こそが、製品全体の信頼性を底上げする唯一の手段です。
Cost : 量産部品のコスト削減（BOM Cost Reduction）
試験合格直後の喜ばしい瞬間を、弊所は「コストダウンの好機」と捉えます。
「抜本的対策」によって支配的なノイズ源が除去された今、初回デフォルトで保険的に実装してきた対策部品が担っていた微細な減衰は不要になるケースが殆どです。
「念のため」と実装されている部品を、理論的根拠をもって『過剰』と判断し未実装にする。
これは、製品の利益率を恒久的に改善し続けるための、価値あるエンジニアリングです。
もう次の工程に進まなければいけないことは十分にわかっています。しかし、試験環境が目の前にある「今」しかそのチャンスはないのです。
弊所は、「合格＝ゴール」という現場の安堵感に流されることなく、量産利益を最大化するための「部品削除に向けた仕上げの検証」を、このタイミングでこそ、あえて提言させて頂きます。
Delivery : リードタイムの短縮（Shortening Lead Time）
開発リードタイムを死守するため、弊所はマージン全反映という「無謀な満点主義」を排します。
大切なのは、前述の「マージン調整」に基づく「性能確保」と「早期リリース」の両立です。その最適な着地点を見極め、提言します。
結び
弊所は、「単なる対策屋」に留まるつもりはございません。
製品の品質（Q）はもちろん、コスト（C）や納期（D）までもマネジメントし、量産工程への橋渡しをスムーズに行うこと。それが、コンサルティングサービスとしての私の責任であると自負しております。
なぜ、これほどまでに踏み込んだ提案ができるのか。
それは、私自身が製品のコンセプト立案から回路設計、放熱問題や製造性を考慮したレイアウト設計、そしてEMC・環境試験までの一貫した開発フローの全工程を自律的に完結させてきた実務経験があるからです。
現場の苦悩も、設計の矜持も、私は深く理解しています。
「単に試験を通す」だけではない、貴社の「ビジネスに資する最適解」を共に導き出せることを願っております。