EMC試験合格への抜本的対策と、得られた大幅なマージンをあえてデチューン（マイナス調整）することが最適解
抜本的対策の詳細説明
Negative Synergy
In simple circuits with ten or fewer components, the causal relationships between noise sources are clear, making identification straightforward.
However, as board complexity increases, multiple noise sources begin to interfere with one another, causing them to lose their independence. This is what we call “Negative Synergy.” In this state—where the specific point you are addressing is constantly impacted by noise from other sources—individual component-based fixes become futile.
You likely follow the fundamental principles of circuit design and apply precise suppression to the most dominant noise source. Yet, you will find that the results are barely noticeable.
The reason is simple: the more noise sources there are, the more the “Negative Synergy” (the negative force) overwhelms your “corrective action” (the positive force). The improvement is essentially overwritten, making it impossible to perceive any reduction.
The measure you took is, without a doubt, the “Right Solution.” However, because the effect remains “invisible” under the weight of other noise, you simply cannot experience the breakthrough you deserve.
“If there were a measurement tool capable of completely isolating interferences and extracting the precise effect of the countermeasure you just applied, you would instantly see that your logic was correct. You could then horizontally deploy that solution and reach a final resolution. Unfortunately, no such instrument exists.”
As a result, your entire logic for EMC suppression collapses. You lose sight of your strategic direction and find yourself trapped within a ‘debugging labyrinth’ with no clear way out.
“The more logical and disciplined an engineer you are, the deeper you will sink into this ‘EMC quagmire’ where fundamental principles seem to fail—and the harder it becomes to find an exit on your own.”
Seal All Leaks Simultaneously!
The key to successful EMC suppression is removing negative factors all at once.
The Leaky Bucket Analogy: Imagine a bucket with multiple holes. No matter how much water you pour in, it continues to leak.
The Trap of Partial Fixes: If there are three leaks—A, B, and C—plugging only one (A) will technically reduce the flow. However, as long as B and C remain open, the problem persists, and the bucket fails to fulfill its purpose.
Achieving Peak Performance: To restore the bucket’s “Maximum Performance” (zero leaks), you must identify and seal all critical points simultaneously.
Positive Synergy
“Linear” Improvement Targeting Isolated Causes:
Countermeasures for isolated and simple noise sources are typically handled by adding components like EMI filters. In these cases, the effectiveness strictly follows the datasheet specifications?such as frequency response curves or “XX dB attenuation at XX Amps.” This is merely a “Linear” improvement, where the result is directly proportional to the component’s rated performance.
Explosive “Non-linear” Results Beyond Prediction:
However, when you eliminate the root causes of Negative Synergy, the outcome far exceeds the “Linear” predictions described above. It triggers an “Explosive Non-linear Effect” where the entire board’s immunity is fundamentally transformed.
A Physical Inevitability Beyond Components:
Why is it explosive? Because the Negative Synergy was already causing non-linear degradation. Removing that negative force naturally unlocks a massive, non-linear surge in performance.
As a seasoned engineer, you likely see the conclusion: this methodology delivers a level of effectiveness that individual noise suppression components simply cannot achieve.
Complexity Breeds Excellence: The Spice Analogy
Positive countermeasures don’t just add up; they create a “Positive Synergy.”
The Spice Metaphor: Think of spices A, B, and C in a curry. While each adds its own flavor, combining all three creates a rich, complex “Umami” that is impossible to achieve by simply adding their individual effects.
Real-World Example: Dramatic Surge in EMC Immunity
Consider three points of “Layout and Routing-Driven Noise Suppression” (A, B, and C) designed to improve ESD (Electrostatic Discharge) immunity.
- Assume each measure contributes 1,000V of immunity on its own. Would the total improvement be a simple sum of 3,000V?
- The answer is no. Because these radical countermeasures create a powerful “Positive Synergy,” the cumulative effect often defies simple addition.
- In practice, A+B might yield 5,000V, while A+B+C could cause immunity to skyrocket to 10,000V.
ここにポエム２を配置すると効果的だと思う
FAQ
What exactly is “Layout and Routing-Driven Noise Suppression”?
It is a methodology that enhances EMC immunity at its core. Instead of relying on add-on components, we identify the specific “pathological areas” vulnerable to noise and eliminate the root cause through strategic layout and routing modifications.
Is this applicable to any type of product or industry?
Yes, in principle, it is applicable to almost any design regardless of the industry, as our approach is based on fundamental physics. However, please note that in circuits with severe physical constraints, the scope of improvement may be limited. We do not guarantee the same level of results for every project.
We already identify causes and apply countermeasures daily. What makes your approach different?
The difference lies in our “analytical perspective” and the “systematic process” we use to reach a resolution—both of which operate on a fundamentally different level. Please refer to the following five key points.
Standard Approach:
Noise entry/exit points (Connectors and external interfaces).
External control terminals of each device (Reset, Interrupt, Enable/Disable pins, etc.).
Our Approach:
Structural vulnerabilities of the entire PCB (Note: We do not focus on noise entry/exit points at all.)
Standard Approach:
Because the input stage is the direct trigger that causes malfunctions.
Because applying countermeasures at the input terminals is considered the “standard” of EMC design.
Our Approach:
Because those “structural vulnerabilities” are the true root cause that weakens noise immunity across both EMI and EMS.
Standard Approach:
Adding off-the-shelf suppression components or modifying circuit constants.
Our Approach:
Eliminating the “structural vulnerabilities” themselves.
“Now, imagine a situation where you have achieved some improvement, yet you still haven’t reached the compliance limit—for example, the 8kV air discharge requirement in an ESD test.”
Standard Approach:
Adding even more suppression components and repeatedly attempting to “reinforce” the board by brute force.
Our Approach:
Searching for other latent “structural vulnerabilities” and horizontally deploying the same radical countermeasures (elimination).
Standard Approach:
Even after adding two or three more components, you likely won’t see any significant breakthrough in effectiveness.
Our Approach:
Because we eliminate the “structural vulnerabilities”—the true root causes—the improvement in noise immunity is directly proportional to each action taken.
While the magnitude of improvement varies by board design, your immunity will increase reliably and significantly with every countermeasure we apply.
大幅なマージンを獲得したEMC対策の実績例
弊所がこれまでに手掛けた対策の一例を紹介します。
静電気試験（ESD）
対策前：0.5kV で誤動作
対策後：15kV クリア（要求規格：8kV）
放射妨害電界強度試験（RE:Radiated Emission）
対策前：合格ラインに対しQP値で-2〜3dB の限界値（不合格リスクが非常に高い）
対策後：-10〜15dB の十分なマージンを確保
■The Reality of the Professional Environment
Back then, I worked for a high-end contract design firm where we handled the entire process from schematics to mass production in rapid 2-3 month cycles. We weren’t a small shop.
Our R&D division had eight groups, each with 5-6 hardware and software engineers.
Our PCB layout and mechanical departments were separate elite units. With over 80 developers and 50 Zuken CR-5000 (SD/BD/PWS) licenses, we were a mid-to-large operation handling mission-critical projects for automotive, medical, telecommunications, and government sectors.
■The Brutal Design Reviews (DR)
Operating as a matrix organization, every failure and piece of know-how was shared across teams.
Our quality checklists were massive.
The Design Reviews after schematics and layout were brutal. A single session with all department leaders lasted at least five hours—and no design ever passed on the first attempt.
All “standard” EMC measures were, of course, already implemented to the highest degree from day one.
■The Elite Layout Team
The PCB layout team consisted of pure professionals. They were so experienced that they could interpret EMC requirements directly from the schematics and implement optimal routing without needing a single instruction.
■当時、設計していた製品の紹介
The Target Product: Professional Image Recorder
| PCB | 8-layer (FR-4), postcard-sized. |
| CPU | 32-bit ARM Core. |
| Memory | Flash ROM, DDR2, External SD Card. |
| Main Processors | FPGA (Xilinx Spartan-3) |
| Interfaces | Ethernet, USB, HDMI, UART. |
| Power | Dual system (AC adapter / Li-ion battery). |
| Display | ~5-inch TFT LCD. |
| Controls | Membrane switches connected via FPC. |
~ The Moment of Truth: The First Test ~
■The Setup: Preliminary Bare-Board Testing
The enclosure wasn’t ready yet, but we conducted preliminary tests on the bare board to gauge our standing.
The LCD and membrane switches were hung loosely. Power was supplied via an AC adapter.
■Initial Results: A Total Disaster
ESD (Contact Discharge): We started at the absolute minimum setting of 500V. One zap, and the system reset instantly. 100% reproducibility.
Radiated Emission: We were failing by +5dB to +8dB over the limit. It wasn’t just a specific frequency spike; the entire spectrum was a mess of protruding peaks across the whole band.
It wasn’t a matter of “fine-tuning” anymore. We were facing a complete engineering roadblock.
■The Reality: This is No Longer an Engineering Problem
The requirement was 8kV Air Discharge.
In the final product, the board would be encased, theoretically avoiding direct contact. However, the LCD frame would undoubtedly crackle with discharge as usual.
Even if we could dodge the air discharge, the exposed metal frames of the external connectors meant there was no escaping the Contact Discharge.
And here we were, failing at a mere 500V.
This wasn’t a level where you could just “fix it” by swapping a few EMI filters or capacitors.
The EMI (Radiated Emission) was equally a nightmare. Since the enclosure was plastic, the shielding effect was zero. I decided to put the emission problem aside for a moment—I had to face the monster in front of me first.
■The Internal Conflict
- We followed every EMC best practice. Why is this happening?
- What was the point of those grueling 5-hour Design Reviews with the ‘Gods of Engineering’ (my seniors) and their confident mandates?
- Realistically, what else is left to do? Where is the space to add even one more component?
- Shielding a plastic case with gaskets for a Class 2 device? That’s nonsense—it would skyrocket the BOM cost and ruin the project’s viability.
- I had a gut feeling: Even if I added 1,000 more noise suppression parts blindly, the immunity wouldn’t budge. I had to change the fundamental approach.
■The Futile “Best Practice” Patchwork
I tried the textbook moves anyway. I changed component values without real conviction. I stacked varistors on top of capacitors (the “piggyback” method) on signal lines.
The result? Zero effect.
The board mocked me with another instant reset at 500V.
■Stepping Back to Think
I asked myself: “What is different about this board compared to the ones that passed before?”
- The components were incredibly dense. The surface layers were so packed you could barely squeeze in a single trace.
- This was our first 8-layer design.
- It was a Class 2 device—no chassis ground to dump the energy into.
- Then, the fundamental question: “Where does the static charge actually go from the point of injection, and exactly how does it trigger a system reset?”
■【THE BREAKTHROUGH】 The Turning Point
I shifted my perspective. I decided—with all due respect to the “Gods” of the Design Review—to test a theory of my own. I implemented a modification at just one single location based on my new hypothesis.
The result? The immunity jumped from 500V to 4kV instantly!
It worked. It was real. I applied the same logic to every other vulnerable point I could identify.
The outcome was beyond compliance: it passed 15kV Air Discharge with ease.
I wanted to push it even further to find the true limit, but I stopped there—I didn’t want to risk destroying the only evaluation board we had.
■The Side Effect: EMI Success
Out of curiosity, I ran the Radiated Emission test again in this state.
Average noise levels had dropped by 10dB. Even at the worst peak (QP value), we had a -5dB margin against the limit.
“Wait, why did this happen?” A -5dB worst-case margin on a bare board was an incredible achievement.
■Stripping Away the “Insurance”
As a final test, I began removing all those “standard” EMC components I had desperately added earlier.
The 15kV immunity remained rock solid. As I suspected, those parts weren’t doing anything.
“This method is far more effective than fighting noise with components.”
Next, I tested EFT/B (Electrical Fast Transient/Burst). Initially, it failed at 500V in a bizarre way (only on the negative side of the normal mode). Now, it cleared 2000V without a flinch.
That “Certain Proof of Effect” I found that day—by testing my own theory at a single point—became the origin of the Radical Optimization services I provide today.
Strategic Margin Adjustment: “De-tuning”
The “massive design margin” created through “Layout and Routing-Driven Noise Suppression” is a “Critical asset”—not only for ensuring product reliability but also for enabling further optimization.
However, attempting to implement every suggested countermeasure in the mass-production board may require a “Complete overhaul of the layout”, risking significant delays in the development schedule.
This is where “Strategic Margin Adjustment” (De-tuning) becomes essential. By strategically “Trimming the excess margin”, we find the “Optimal balance between compliance and man-hours” required for design modifications.
イメージ図
As shown in the diagram above, there is a clear “Trade-off” between achieving a ‘massive design margin’ and ‘minimizing “Development lead time”.’
We visualize this correlation “To help you identify” the “Optimal landing point”—balancing technical robustness with your specific business requirements and project schedules.
まとめ：EMC最適解がもたらす価値
圧倒的な安定度
弊所が提供するEMCコンサルティングは、従来の「対症療法」とは一線を画します
EMC試験において、合格と不合格を繰り返す不安定な状況に苦慮された経験はないでしょうか。フェライトコア等の対策部品に頼る手法は、その減衰効果が限定的であり、わずかな個体差や環境変化で合格ラインを下回るリスクが常に内在しています。
弊所は、ノイズの発生機序そのものを物理的に制御するアプローチをとります。それにより、環境変化に左右されない「圧倒的な安定度」を設計段階から担保します。
本質的なQCD向上
Quality : ロバスト設計：バラツキに強い設計（Robust Design）
弊所が提唱する「抜本的対策」は、ノイズの源流に直接介入します。
これにより、個々の部品が持つ定数誤差や温度特性による影響を最小限に抑え込み、部品の個体差によってノイズ耐性が不安定になるフェーズを脱却します。
結果として、量産期間が長期に及ぶ中で発生する「製造バラツキ」に対しても、極めて高い耐性を持つ設計（ロバスト設計）が確保されます。
設計品質の根本的な向上こそが、製品全体の信頼性を底上げする唯一の手段です。
Cost : 量産部品のコスト削減（BOM Cost Reduction）
試験合格直後の喜ばしい瞬間を、弊所は「コストダウンの好機」と捉えます。
「抜本的対策」によって支配的なノイズ源が除去された今、初回デフォルトで保険的に実装してきた対策部品が担っていた微細な減衰は不要になるケースが殆どです。
「念のため」と実装されている部品を、理論的根拠をもって『過剰』と判断し未実装にする。
これは、製品の利益率を恒久的に改善し続けるための、価値あるエンジニアリングです。
もう次の工程に進まなければいけないことは十分にわかっています。しかし、試験環境が目の前にある「今」しかそのチャンスはないのです。
弊所は、「合格＝ゴール」という現場の安堵感に流されることなく、量産利益を最大化するための「部品削除に向けた仕上げの検証」を、このタイミングでこそ、あえて提言させて頂きます。
Delivery : リードタイムの短縮（Shortening Lead Time）
開発リードタイムを死守するため、弊所はマージン全反映という「無謀な満点主義」を排します。
大切なのは、前述の「マージン調整」に基づく「性能確保」と「早期リリース」の両立です。その最適な着地点を見極め、提言します。
結び
弊所は、「単なる対策屋」に留まるつもりはございません。
製品の品質（Q）はもちろん、コスト（C）や納期（D）までもマネジメントし、量産工程への橋渡しをスムーズに行うこと。それが、コンサルティングサービスとしての私の責任であると自負しております。
なぜ、これほどまでに踏み込んだ提案ができるのか。
それは、私自身が製品のコンセプト立案から回路設計、放熱問題や製造性を考慮したレイアウト設計、そしてEMC・環境試験までの一貫した開発フローの全工程を自律的に完結させてきた実務経験があるからです。
現場の苦悩も、設計の矜持も、私は深く理解しています。
「単に試験を通す」だけではない、貴社の「ビジネスに資する最適解」を共に導き出せることを願っております。